1. Technical Field
The present invention generally relates to a semiconductor device, more particularly relates to a non-volatile memory device.
2. Related Art
A non-volatile memory device means a memory device in which stored data is remained though a power is not supplied, and is divided into an electric charge trap-type memory device and a floating gate-type device. Here, the electric charge trap-type memory device stores data by trapping or discharging electric charges to a deep level trap site in a electric charge trap layer, and the floating gate-type memory device stores data by storing or discharging electric charges to a conductive band of a floating gate.
Hereinafter, structure of the conventional non-volatile memory device will be described in detail with reference to drawings.
FIG. 1a to FIG. 1c illustrate a layout and a section view of the conventional non-volatile memory device. FIG. 1a shows a layout of a cell array, FIG. 1B illustrates a layout of each of areas of a substrate, and FIG. 1c shows a cross section of a memory cell.
As shown in FIG. 1a to FIG. 1c, the conventional non-volatile memory device includes memory blocks MB1 and MB2 and a common source line CSL located between neighbored memory blocks MB1 and MB2. Here, each of the memory blocks MB1 and MB2 includes a drain select line DSL, word lines WL and a source select line SSL extended parallel in a second direction II-II′.
A memory device includes an isolation layer 17 formed in a field area F of a substrate 10, and thus an active area A extended parallel in a first direction I-I′ is defined. The memory device includes a tunnel insulating layer 11, a floating gate 12, an electric charge blocking layer 13 and a control gate 14 (i.e., 14(WL)), an interlayer dielectric layer 15 and bit lines 16 (i.e., 16(BL)) stacked in sequence on the substrate 10
The active area A corresponds one-to-one to the bit line BL, and the bit lines BL are coupled to the active areas A through a bit line contact plug CT1 and CT2, respectively.
Accordingly, both of width of the active area A and width of the bit line BL should be reduced, so as to enhance integrity of the memory device. However, a gap-fill process has its limit to reduce the width of the active area A in a process of forming the isolation layer 17 by which the active area A is defined.